The present invention relates to a silicon carbide MOS semiconductor device, such as a field-effect transistor (hereinafter referred to as xe2x80x9cMOSFETxe2x80x9d) having a gate of metal-oxide-semiconductor structure, which device uses silicon carbide (hereinafter referred to as xe2x80x9cSiCxe2x80x9d) as a semiconductor material. The present invention also relates to a method for manufacturing such MOS semiconductor devices.
SiC is a semiconductor material that has been highly expected to be used in power semiconductor devices or semiconductor devices for high-temperature use. Among various types of power semiconductor devices, those called MOSFET have particularly simple structures, and may be used in a considerably wide range of applications. Accordingly, more and more studies have been conducted on fabrication of MOSFET using SiC. Another reason for extensive development and studies of SiC MOSFET is that a silicon dioxide film is grown on SiC (hereinafter referred to as xe2x80x9cSiO2 filmxe2x80x9d) thereon through thermal oxidation, as in the case of silicon (hereinafter referred to as Si), and therefore the same process for manufacturing MOSFET using Si as a semiconductor material may be used for manufacturing SiC MOSFET. Some research groups or researchers including the inventor of the present invention have fabricated MOSFETs using SiC, and reported their characteristics.
The SiC MOSFET, however, suffers from an extremely low mobility of electrons in an inversion layer formed in its surface. SiC is known as having crystalline polymorphism, namely, SiC crystallizes into two or more forms having different structures. Single crystals of SiC currently available in the market include 6Hxe2x80x94SiC and 4Hxe2x80x94SiC, both of which are alpha-phase SiC in which a zinc-blend structure and a wurtzite structure are superposed on each other. Of these single crystals, 4Hxe2x80x94SiC has a relatively higher electron mobility than 6Hxe2x80x94SiC, and is thus more expected to be applied to power devices.
FIG. 10 is a cross-sectional view of a vertical MOSFET having a general DMOS structure. In FIG. 10, a p base region 12 is formed in a surface layer of an n drift layer 11a, and an n+ source region 13 is formed in the p base region 12. A gate electrode 16 is formed on a gate insulating film 15, over a part of the surface of the p base region 12 that is interposed between the n+ source region 13 and an exposed surface portion of the n drift layer 11a. Also, a source electrode 17 is formed in contact with surfaces of both the n+ source region 13 and the p base region 12a, and a drain electrode 18 is formed in contact with the rear surface of an n+ drain region 14.
In the operation of the MOSFET as described above, when a positive voltage is applied to the gate electrode 16, an inversion layer is induced in a surface layer of the p base region 12 right under the gate insulating film 15, so that current flows between the source electrode 17 and the drain electrode 18. If the positive voltage to the gate electrode 16 is removed, the inversion layer right under the gate insulating film 15 disappears, and a depletion layer spreads out, thus blocking current flow through the p base region 12.
As described above, currently available SiC n-channel MOSFET suffers from a low mobility of electrons in its inversion layer. In a 6Hxe2x80x94SiC MOSFET, for example, an inversion layer has electron mobility of about 70 cm2/V.s (as reported in Lipkin, L. A. and Palmour, J. W.: J. Electronic. Materials Vol. 25 (1996) p.909). In a MOSFET using 4Hxe2x80x94SiC and fabricated under the same conditions, on the other hand, only a considerably low electron mobility, more specifically, 10 cm2/V.s or lower, can be obtained. In recent studies, the inventor and others found that the electron mobility of 4Hxe2x80x94SiC MOSFET may be increased to 20 cm2/V.s at the most, even with various changes or improvements in the manufacturing process (as reported in IEEE Electron Device lett. Vol. 19 (1998), p.244).
It follows that the electron mobility of 4Hxe2x80x94SiC devices is significantly lower than that of 6Hxe2x80x94SiC devices, and even 6Hxe2x80x94SiC devices need to provide a higher mobility. Thus, such semiconductor devices that take advantage of low resistance as an inherent property of SiC crystal have not yet been successfully fabricated.
To overcome the above problem, there has been reported some semiconductor devices called ACCUFET, wherein a low-concentration n-type layer is formed below a gate electrode, and an accumulation layer, rather than an inversion layer, is used as a conduction layer.
FIG. 11 is a cross-sectional view of a part of a planar-type ACCUFET proposed by Shenoy et al. (refer to Shenoy, P. M. and Baliga, B. J.: Materials Science Forum Vols. 264-268 (1998) p.993).
In the ACCUFET of FIG. 11, an n channel region 30, rather than a p type region, is formed in a surface layer right under a gate insulating film 25. When a positive voltage is applied to a gate electrode 26, an accumulation layer is induced in a surface layer of the n channel region 30 right under the gate insulating film 25, so that current flows between a source electrode 27 deposited on an n+ source region 23, and a drain electrode 28 deposited on the rear surface of an n+ drain region 24. When the voltage to the gate electrode 26 is removed, the accumulation layer right under the gate insulating film 25 disappears, and a depletion layer spreads out, thus blocking current flow through the accumulation layer. The ACCUFET using 6Hxe2x80x94SiC as a semiconductor material provides an electron mobility of 81 cm2/V.s.
FIG. 12 is a cross-sectional view showing a part of another example of ACCUFET proposed by Hara (refer to Hara, K.: Materials Science Form Vols. 264-268 (1988) p.901). This example is a UMOSFET having a trench structure, and basically identical with the ACCUFET of FIG. 11 as described above. In this example, too, an n channel region 40 in the form of an n type epitaxial layer is formed in the surface of the SiC substrate, to provide an accumulator layer. Upon application of a positive voltage to a gate electrode 36, an accumulation layer is induced in the n channel region 40, so that current flows between a source electrode 37 that contacts with an n+ source region 33, and a drain electrode 38 deposited on the rear surface of an n+ drain region 34.
The ACCUFET of FIG. 11 and the UMOSFET of FIG. 12, however, are typically depletion type (normally-on type) transistors in which current flows even when no voltage (0V) is applied to the gate electrode 26, 36. It is thus difficult to produce the above transistors to be of enhancement type (normally-off type), due to restrictions imposed on the structures of the devices.
It is therefore an object of the present invention to provide an normally-off type or enhancement type SiC MOS semiconductor device which has a high electron mobility of a channel region to assure a low ON-state resistance, and which can be easily manufactured. It is another object to provide a method for manufacturing such SiC MOS semiconductor devices.
To accomplish the above object, the present invention provides a silicon carbide n channel MOS semiconductor device, comprising: a semiconductor substrate comprising silicon carbide, the substrate including a p base region, an n+ source region and an n+ drain region; a gate insulating film formed on a surface of the p base region; a gate electrode provided on the gate insulating film; and first and second main electrodes that allow current to flow therebetween; wherein current flowing between the first and second main electrodes is controlled by controlling an electron concentration of an inversion layer that is induced in a surface layer of the p base region located under the gate insulating film when a positive voltage is applied to the gate electrode; and wherein the effective acceptor concentration in the vicinity of an interface between the p base region and the gate insulating film is in a range of 1xc3x971013 to 1xc3x971016 cmxe2x88x923.
In the course of studies on silicon carbide MOSFET, the inventor of the present invention found that the electron mobility of a channel region can be improved by forming a low-concentration region in a surface layer of a semiconductor substrate of the n channel MOSFET.
FIG. 2 is a graph showing results of experiments conducted on silicon carbide n channel MOSFET, more specifically, the dependence of the acceptor concentration of a p base region on the mobility of the channel region. In FIG. 2, the horizontal axis indicates the acceptor concentration on a logarithm scale, and the vertical indicates the mobility of the inversion layer, with respect to two crystalline forms (6Hxe2x80x94SiC and 4Hxe2x80x94SiC) of silicon carbide.
It will be understood from FIG. 2 that the mobility is greatly dependent upon the acceptor concentration, namely, the mobility decreases as the acceptor concentration increases. Where the acceptor concentration is 1xc3x971016 cmxe2x88x923 or lower, for example, the 6Hxe2x80x94SiC device provides a mobility of 80 cm2V.s or higher, and the 4Hxe2x80x94SiC device provides a mobility of 30 cm2V.s or higher.
While no data is shown for the acceptor concentration of 1xc3x971014 cmxe2x88x923 or lower, the mobility is supposed to be saturated or maintained at a high level in the range lower than 1xc3x971014 cmxe2x88x923. So far, no method is available for realizing the impurity concentration of less than 1xc3x971013 cmxe2x88x923 with sufficient stability.
If the entire p base region of the MOSFET is formed with a low concentration of 1xc3x9710 16 cmxe2x88x923 or lower, the resistance of the p base region is considerably increased, causing secondary problems such as latch-up. Such problems can be solved by forming only a surface layer of the p base region that is very close to the substrate surface with a low impurity concentration while forming the inner or deeper portion of the region with a high concentration.
Quantitatively, the total amount x per unit area of donor impurities introduced into the surface layer of the p base region is preferably controlled to be a range represented by:
1xc3x971011 cmxe2x88x922 less than x less than 5QB/q,
QB=(4∈o∈s"PHgr"BNA)xc2xd
where ∈o is a dielectric constant in vacuum, ∈s is a dielectric constant of silicon carbide, "PHgr"B is an energy difference between an intrinsic Fermi level and a Fermi level of silicon carbide, NA is an acceptor concentration of the p base region before implantation of donor ions, and q is an intrinsic charge. With the amount of impurities thus controlled, a sufficiently large mobility can be obtained in an inversion layer of the MOSFET, as described later in some embodiments of the invention.
The present invention also provides a method for manufacturing such a silicon carbide n channel MOS semiconductor device as described above, wherein current flowing between the two main electrodes is controlled by controlling an electron concentration of an inversion layer that is induced in a surface layer of the p base region under the gate insulating film upon application of a positive voltage to the gate electrode, and wherein the effective acceptor concentration of the p base region in the vicinity of the interface between the p base region and the gate insulating film is controlled to be in a range of 1xc3x971013 to 1xc3x971016 cmxe2x88x923. In the manufacturing method of the invention, the acceptor concentration of the surface layer of the p base region is made lower than that of the inner or deeper part of the p base region by controlling the acceleration voltage and dose amount during ion implantation for forming the surface layer of the p base region, or implanting ions of donor impurities into a surface layer of the p base region, or forming a low-concentration layer by epitaxial growth as a surface layer of the p base region so that the acceptor concentration of the epitaxial layer becomes lower than that of the inner portion of the p base region.
Where ions of the donor impurities are implanted into the surface layer of the p base region, the dose amount x is preferably controlled to be in a range represented by:
1xc3x971011 cmxe2x88x922 less than x less than 5QB/q,
QB=(4∈o∈s"PHgr"BNA)xc2xd
where ∈o, ∈s, "PHgr"B, NA, and q are the same as those as indicated above. With the dose amount thus controlled, the inversion layer achieves a sufficiently high mobility, as described later in the embodiments of the invention.
The donor impurities as indicated above may be nitrogen or phosphorous.
The manufacturing method may further include a step of conducting heat treatment for activating the impurities introduced by ion implantation. In particular, the heat treatment is preferably conducted at a temperature of 1000 to 1500xc2x0 C. In this case, the activation rate of the impurities introduced through ion implantation is increased, making it possible to reduce the amount of ions to be implanted.